Zajednički odjel za elektroničke elemente / poluvodičke integrirane sklopove (ED15/SSC37) i Odjel za električne krugove i sustave (CAS04) Hrvatske sekcije IEEE poziva Vas na predavanje:
Predictive Analytics for Nanometer Technologies
koje će održati Dr. Rajiv Joshi (IBM, T. J. Watson Research Center, Yorktown Heights, NY). Predavanje će se održati u srijedu 7. srpnja 2026. s početkom u 10:00 putem MS Teams platforme. Poveznica za pristup predavanju nalazi se ovdje.
Predviđeno trajanje predavanje s raspravom je 60 minuta. Predavanje je otvoreno za sve zainteresirane, a posebno pozivamo studente. Više o predavaču i predavanju možete pročitati u opširnijem sadržaju obavijesti.
Abstract:
As semiconductor technology enters the sub-5nm era, geometry, process, voltage, and temperature (PVT) variability in devices can affect the performance, functionality, and power of circuits, especially in new Artificial Intelligent (AI) accelerators. This is where predictive failure analytics is extremely critical. It can identify the failure issues related to logic and memory circuits and drive the circuits in the energy-efficient area. This talk describes how key statistical techniques and new algorithms can be effectively used to analyze and build robust circuits. These algorithms can be used to analyze decoders, latches, and volatile as well as non-volatile memories. In addition, how these methodologies can be extended to “reliability prediction” with “hardware corroboration”. Also, logistic regression-based machine learning (ML) techniques are employed for modeling the circuit response and speeding up the Important Sampling techniques. To avoid overfitting, a cross-validation-based regularization framework for ordered feature selection is demonstrated. Also, techniques to generate accurate parasitic capacitance modeling along with PVT variations for sub-22nm technologies and their incorporation into a physics-based statistical analysis methodology for accurate Vmin analysis are described. Using such innovative techniques device mismatches in memory and their impact on circuit performance in Technology CAD (TCAD) are highlighted. Finally, the talk summarizes important issues in this field.
Biography:
Dr. Rajiv V. Joshi is an IEEE Life Fellow, winner of the prestigious IEEE Daniel Noble award, IEEE Circuit and System Society Vice President of Industry, and a key technical lead/Research Scientist at T. J. Watson Research Center, IBM. He received his B. Tech IIT (Bombay, India), M.S. (MIT), and Dr. Eng. Sc. (Columbia University). He has successfully led innovations in technology, memories (SRAM, DRAM, and others), and predictive analytic techniques for yield prediction for IBM Server Groups and their products. His statistical techniques are tailored for machine learning and AI, which are licensed and commercialized. His memory innovations and work are used in both IBM P and Z servers. His innovations set IBM’s leadership across the globe. He received 7 Outstanding Technical Achievement (OTAs), 3 highest Corporate Patent Portfolio awards for contributions in interconnect technologies, holds 73 invention plateaus, has over 300 US and over 450 international patents covering front-end and back-end of the line processes, structures, volatile and non-volatile memories, Compute in Memory structures, machine learning algorithms, and quantum computing, and over 450 international patents. He has authored and co-authored over 280 refereed papers, delivered over 70 invited/keynote talks, and given several Seminars. He received the NY IP Law Association's Inventor of the Year award in Feb. 2020. He is a Mercator Fellow at the University of Siegen, Germany. He received an industrial pioneer award in 2014 from the IEEE Circuits and Systems Society. He received the Best Editor Award from the IEEE TVLSI journal. He was inducted into the New Jersey Inventor Hall of Fame in Aug 2014. He won the Mehboob Khan Award two times from Semiconductor Research Corporation. He won several best paper awards from ISSCC 1992, VMIC 1998, ICCAD 2009, and ISQED 2014. He is a member of the IBM Academy of Technology and a master inventor. He serves on the Board of Governors for IEEE CAS as an industrial liaison. He served on EC for DAC, ISLPED, CICC, ISCAS, AICAS, and APCCAS (2023) committees, as well as the AE of TCAS I and TVLSI. He served as a Distinguished Lecturer for IEEE CAS, CEDA, and EDS societies. He is an ISQED and World Technology Network fellow and a distinguished alumnus of IIT Bombay. He served on the executive advisory committee for the Center for 3D Ferroelectric and Microelectronics at Penn State. He serves as an IEEE CAS VP-industry and CAS Ambassador to India and involved in STEM activities for underprivileged kids in India.





