Poziv na online IEEE predavanje: Full...

Zajednički odjel za elektroničke elemente / poluvodičke integrirane sklopove (ED15/SSC37) Hrvatske sekcije IEEE poziva Vas na online predavanje:                              

Full chip-level verification of electrostatic discharge robustness of integrated circuits using graph theory

koje će održati Vlatko Galić, mag. ing. sa Sveučilišta u Zagrebu Fakulteta elektrotehnike i računarstva. Predavanje će se održati online u utorak 19. listopada 2021. s početkom u 10:15 sati putem MS Teams platforme. Poveznica za pristup predavanju nalazi se ovdje.

Predviđeno trajanje predavanje s raspravom je 45 minuta. Predavanje je otvoreno za sve zainteresirane, a posebno pozivamo studente. Više o predavaču i predavanju možete pročitati u opširnijem sadržaju obavijesti.



Electrostatic Discharge (ESD) is one of the biggest reliability issues of the semiconductor industry, as the ESD damage can cause a total circuit failure or it can leave latent defects in Integrated Circuits (IC). Several papers have already proved that ESD is a multibillion-dollar problem, as well as a killing factor for time-to-market for any new product in development. To remedy this issue several measuring and characterization methods were invented and standardized to help tackling the growing ESD problem, which are described in this presentation. Furthermore, some protection strategies are shown. One of the major ways used to battle the ESD issue is by using the ESD automatic verification tools. These tools enable users to simulate maximum ESD levels that the IC can handle and possibly solve the issue pre-tapeout. In this presentation, a new ESD verification flow is proposed. The presented methodology uses piecewise linear (PWL) models based on transmission line pulsing (TLP) measurements to ascertain the level of ESD robustness of ICs and to detect ESD current paths. The models are empirical and scalable with all physical parameters present in the used technology. This flow is based on graph-theory Floyd-Warshall (FW) algorithm. The output of the proposed flow is an individual current-voltage (IV) curve between any pin-to-pin combination present in the IC. The flow simultaneously uses custom made tool ESDh and a commercial tool Magwel ESDi for finding failure paths, devices and ESD stress levels, according to Human Body Model (HBM).



Vlatko Galić graduated at the Faculty of Electrical Engineering and Computing at the University of Zagreb in 2016, with the final thesis entitled “Characterization of Differential Attenuator Structures for High-Voltage Measuring Systems". Upon graduation, he received a title of Master of Science in Electrical engineering and information technology. After graduating, he did a yearlong internship in ON Semiconductor in Belgium focusing on ESD simulations. He started his PhD in 2018 as a Research Associate and later a Teaching Assistant with the Department of electronics, microelectronics, computer and intelligent systems, at the Faculty of Electrical Engineering and Computing, under the supervision of prof. Adrijan Barić. He is currently working as a PhD researcher on the project “MUNJA”, funded by ON Semiconductor Belgium.

Autor: Mirko Poljak
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