Hrvatska sekcija IEEE, Odjel za električne krugove i sustave (CAS) poziva vas na predavanje
"The rise of new semiconductor markets and importance of chip-package interaction in technology development"
koje će održati dr. sc. Andrej Ivanković (Infineon, Austria) u petak, 12. siječnja 2018. godine, u 12.15 sati u Sivoj vijećnici na Fakultetu elektrotehnike i računarstva u Zagrebu.
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This presentation will be split into two parts: ongoing semiconductor market shifts and new applications with focus on advanced semiconductor packaging and chip-package interaction based technology development.
Future semiconductor industry drivers are expected to be fragmented and more diverse than in the mobile era. Scaling continues, but functionality and system level features are becoming increasingly important for product differentiation. The future brings the Internet of Things, the semiconductorization of the automotive industry, 5G connectivity, augmented & virtual reality and artificial intelligence. In such an environment, advanced packaging is transforming from follower of scaling technology nodes to enabler of future semiconductor applications and products, having direct impact on product success rates. Heterogeneous integration of multiple dies from the latest to legacy front-end nodes, involving a mixture of latest technology high density interconnects (Intel EMIB, Fan-Out WLP, TSV) to lower cost mature interconnects (Flip Chip, leadframe), at high levels of customization is the future of semiconductor packaging. In this section, an overview of the latest market and technology developments in the field of advanced packaging will be given.
Vertical stacking of chips (3D IC stacking with TSVs, microbumps) is a new packaging technology that has been in high volume production for several years with first products coming from Samsung, AMD and NVIDIA. However, chip-package interaction remains one of the key challenges. In order to support 3D IC technology development, a chip-package interaction methodology has been developed involving stress sensor selection, calibration and finite element simulations with impact on IC and package design changes. This methodology has been successfully deployed to detect, explain and resolve the underfill-microbump interaction mechanism causing FET current shifts of 40% above specification.
Andrej Ivankovic received his master’s degree in Electrical Engineering, with specialization in Industrial Electronics from the University of Zagreb, Croatia and a PhD in Mechanical Engineering from KU Leuven, Belgium. He started as an intern at ON Semiconductor performing reliability tests, failure analysis and characterization of power electronics and packages. The following 4 years he worked as an R&D engineer at microelectronics institute IMEC Belgium on the development of 3D IC technology, focusing on electrical and thermo-mechanical issues of 3D stacking and packaging. During this time he also worked at GLOBALFOUNDRIES as an external researcher. Interested in market impacts, Andrej continued his career as a Technology & Market Analyst, in the Advanced Packaging and Semiconductor Manufacturing team, at Yole Développement the «More than Moore» market research and strategy consulting company. He is currently employed at Infineon Austria in the role of Requirement and Verification Manager. Andrej has regularly presented at international conferences authoring and co-authoring >20 papers and 1 patent.