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Elektromagnetska kompatibilnost (engl. Electromagnetic Compatibility, skr. EMC) definirana je kao sposobnost uređaja, opreme ili sustava da zadovoljavajuće radi u svom elektromagnetskom okruženju, tj. da radi u namijenjenim operacijskim uvijetima sa zadanim nivoima učinkovitosti bez pogoršanja zbog elektromagnetskih međudjelovanja, kao i da svojim radom ne uzrokuje neželjene elektromagnetske smetnje bilo čemu u tom okruženju.
Poboljšanje elektromagnetske kompatibilnosti uključuje rad u sljedećim područjima:
Razvoj inženjerskih standarda
Razvoj numeričkih modela
Tehnike mjerenja i testne procedure
Instrumenti za mjerenje
Karakteristike sustava i opreme, kao što su osjetljivost (otpornost), povredljivost, odgovarajući efekti širenja, i subjektivni efekti
Unaprijeđenje tehnika i komponenata
Edukacija o elektromagnetskoj kompatibilnosti
Studije o podrijetlu interferencija, umjetnih, kao i prirodnih, i njihove klasifikacije
EM-zaštita
Tehnike štićenja
Nuspojave djelovanja elektromagnetske energije
Znanstvene, tehničke, industrijske, profesionalne ili neke druge aktivnosti, koje dopridonose ovom području, ili koriste tehnike ili proizvode ovog područja.
IEEE EMC Society organizira predavanja istaknutog predavača(Distinguished Lecturer) profesora Joungho Kim iz KAIST-a (KoreaAdvanced Institute of Science and Technology) u formi online seminara.Seminar će se održati 21.7.2010. s početkom u 9:00 i trajanjem do 12:00po *američkom centralnom vremenu* (Central Daylight Saving TimeGMT-06:00).
U prilogu su sažeci predavanja i upute za spajanje.
Srdačan pozdrav,
Antonio Šarolić
Predsjednik Odjela za elektromagnetsku kompatibilnost Hrvatske sekcije IEEE
(IEEE EMCS Croatia Chapter)
Poštovani članovi IEEE EMC Society
IEEE EMC Society organizira predavanja istaknutog predavača(Distinguished Lecturer) profesora Joungho Kim iz KAIST-a (KoreaAdvanced Institute of Science and Technology) u formi online seminara.Seminar će se održati 21.7.2010. s početkom u 9:00 i trajanjem do 12:00po *američkom centralnom vremenu* (Central Daylight Saving TimeGMT-06:00).
Recently, process dimensions of Silicon based semiconductordevices are reaching less than 20 nm scale. However, it sufferssignificant technical and business challenges including enlarged leakagecurrent and considerable increase of investment budget. As a result, newTSV (Through Silicon Via) based 3D IC technology is emerging as apromising next generation IC technology in both semiconductor industryand academia. In the 3D IC, very thin semiconductor dies of less than 30um are vertical stacked to minimize the package size and to maximize thesemiconductor system performances. In the 3D IC, TSV is becoming themost critical vertical interconnection structure between thesemiconductor dies. Around world, most of the semiconductor companiesincluding Intel, IBM, TI, AMD and Qualcomm are seriously considering theTSV based 3D IC as a future direction of the semiconductor integrationtechnology. In the TSV based 3D IC, signal integrity is becoming themajor design obstacle due to the high frequency loss, coupling, andelectromagnetic radiation, while more than thousand of vertical andlateral interconnections are routed in a tiny 3D space. It could be evenmore serious in 3D IC for the applications of high-density andmulti-function mobile multimedia, computing, and communication systemplatforms. In this talk, new modeling, measurement, design, and analysisapproaches will be introduced in order to enhance the performance andreliability of the 3D IC.
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2) Central Time 10:30 AM - 12:00 PM
Title: "Power Integrity of SiP (System-In-Package)"
Abstract:
Power supply noise by digital switching is becoming the majorsource of electromagnetic noise generation and coupling in semiconductorsystems. It could be even more serious in 3D SiP for high-density andmulti-function mobile multimedia, computing, and communication systemplatforms. In this talk, new modeling, design, and analysis approacheswill be introduced with the consideration of the power integrity. Theunique methods are based on simultaneous and hierarchical chip-packageco-design and modeling in order to offer cost effective designsolutions. In particular, we will shown novel design methods and testresults including thin film capacitor and EBG structures to minimize thepower supply noise generation and coupling.
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Dr. Joungho Kim received B.S. and M.S. degrees in electrical engineeringfrom Seoul National University, Seoul, Korea, in 1984 and 1986,respectively, and Ph.D degree in electrical engineering from theUniversity of Michigan, Ann Arbor, in 1993. In 1994, he joined MemoryDivision of Samsung Electronics, where he was engaged in Gbit-scale DRAMdesign. In 1996, he moved to KAIST (Korea Advanced Institute of Scienceand Technology). He is currently a Professor at Electrical Engineeringand Computer Science Department, and the group director of ConvergenceDevice and System Group. Since joining KAIST, his research centers onEMC modeling, design, and measurement methodologies of 3D IC,System-in-Package(SiP), and multi-layer PCB. Especially, his majorresearch topic is focused on chip-package co-design and simulation forsignal integrity, power integrity, ground integrity, timing integrity,and radiated emission of 3D IC and SiP. He has successfully demonstratedlow noise and high performance designs of numerous SiP's for wirelesscommunication applications such as ZigBee, T-DMB, NFC, and UWB.Recently, he is playing a leading role in a national project, OLEV(Online Electrical Vehicle) project, for EMI and EMF reduction design.He was on a sabbatical leave during an academic year from 2001 to 2002at Silicon Image Inc., Sunnyvale CA. He was responsible for low noisepackage designs for SATA, FC, HDMI, and Panel Link SerDes devices. Hehas authored and co-authored over 300 technical papers published atrefereed journals and conference proceedings in modeling, design, andmeasurement of 3D IC, SiP, and PCB. Also, he has given more than 130invited talks and tutorials at the academia and the related industries.He received Outstanding Academic Achievement Faculty Award of KAIST in2006, Best Faculty Research Award of KAIST in 2008, National 100 BestProject Award in 2009, and KAIST International Collaboration Award in2010, respectively. Dr. Joungho Kim was the symposium chair of IEEEEDAPS 2008 Symposium. He is appointed as an IEEE EMC societydistinguished lecturer in a period from 2009-2011. He receivedTechnology Achievement Award from IEEE Electromagnetic Society in 2010.Currently, he is an associated editor of the IEEE Transactions ofElectromagnetic Compatibility, and serving as a guest editor of thespecial issue in the IEEE Transactions of Electromagnetic Compatibilityfor PCB level signal integrity, power integrity, and EMI/EMC, and, alsoas a guest editor of the special issue in the IEEE Transactions ofAdvanced Packaging for TSV (Through-Silicon-Via).