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"Memory Controller Performance for Smartphone Workloads"
Goran Narančić, M.A.Sc.
University of Toronto
Predavanje će bit održano u četvrtak 14. veljače 2013. godine s početkom u 14:15 u Sivoj vijećnici Fakulteta elektrotehnike i računarstva.
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This lecture will present a methodology for exploration of the main memory performance for smartphone workloads. The high speeds of modern CPUs require large amounts of data, and the lagging DRAM speeds present a crucial challenge. This problem is further compounded in the smartphones by the data requirements of the many commonly used applications (ex. video recording/playback), while their small size limits the available hardware. The central part of a DRAM subsystem is the memory controller, which receives the data requests and issues commands to the memory chips to service them.
We describe a trace-based methodology which uses a software implementation to mimic the behaviour of specialized hardware accelerators. Our methodology is based on the dataflow information from the original application to maintain the relationships between requests. We developed a Video Conference Workload (VCW) to model typical smartphone usage. Different address mapping schemes and memory controllers are studied and compared to explore the memory controller behaviour for workloads typical to a smartphone-like system.
Goran Narančić received M.A.Sc. in Computer Engineering at University of Toronto with prof. Moshovos as supervisor. There his research concentrated on memory controller design for smartphone platforms. Before working in computer architecture, he received a M.Sc. in Computer Science from Faculty of Electrical Engineering at the University of Zagreb, where his supervisor was prof. Srbljić. He has a wide area of research interests, which range from computer architecture through programming languages, distributed computing and artificial intelligence.